The present invention relates to display device fabrication, and in particular a method for fabricating an array substrate.
Recently, in order to fulfill the requirements of high-speed image processing and high quality image displays, flat panel displays, such as color liquid crystal displays (LCDs) have become popular. LCDs have an upper and a lower substrate with electrodes thereon. These substrates are sealed with adhesive materials, and a liquid crystal material is sealed between these two substrates. Prior to liquid crystal injection spacers are sprayed between the substrates in order to maintain a constant distance therebetween. TFTs are typically formed above the lower substrate as switching devices. Each TFT has a gate electrode connected to a scanning line, a drain electrode connected with a signal line, and a source electrode connected to a pixel electrode. The lower substrate is also called an active matrix substrate. The upper substrate includes a color filter and a common electrode. Elements formed over these substrates are typically defined by performing several photolithography steps. Thus, the cost and time required for array substrate fabrication is related to the number of photolithography steps.
FIGS. 1A-1F are schematic diagrams showing a conventional method for fabricating an array substrate using six photolithography steps. In this specification, the term “photolithography” is defined to include the fabrication steps of resist coating, exposure with a patterned mask, resist development, resist etching, and remaining resist removal all of which are well known in the art and are collectively referred to as photolithography hereafter.
In FIG. 1A, a metal layer formed on a substrate 104 is first patterned by a first photolithography step to form a patterned gate 100 for a thin film transistor and a conductive line 102. The conductive line 102 can function as a gate line (i.e. scan line) or data line (i.e. signal line) and is formed over the substrate 104 in continuous manner.
In FIG. 1B, an insulating layer 106, semiconductor layer 108, and ohmic contact layer 110 are then blanketly formed over the substrate 104 in sequence and are then patterned by a second photolithography step to define a patterned semiconductor layer 108 and ohmic contact layer 110 over the portion of the insulating layer 106 over the gate 100.
In FIG. 1C, a via hole 112 is then formed passing through the insulating layer 106 at a place relative to the conductive line 102 by a third photolithography step.
In FIG. 1D, another metal layer is blanketly formed over the substrate 104 and then patterned by a fourth photolithography step to form a conductive layer 114 overlying the conductive layer 102 and the patterned ohmic contact layer 110 and semiconductor layer 108 adjacent to the gate 100. In the fourth photolithography step, the metal layer 114, ohmic contact layer 110, and portions of the semiconductor layer 108 adjacent to the gate 110 are simultaneously etched away to thereby form a recess 116. A thin film transistor is thus fabricated over the substrate.
In FIG. 1E, a passivation layer 118 is then blanketly formed over the structure illustrated in FIG. 1D and then patterned by a fifth photolithography step to form a patterned passivation layer 118 with a via hole 120 which exposes a portion of the metal layer 114 at suitable position, as a contact area.
In FIG. 1F, a transparent conductive layer 122 is then formed in the via hole 120 and over the passivation layer 118 and then patterned by a sixth photolithography step to form patterned transparent conductive layer 122 over the passivation layer 118 to function as a pixel electrode. Thus, fabrication of an array substrate is complete.
Generally, the conductive line for functioning as a scan or signal line is formed of a continuous conductive layer. With LCD panel size increasing, scan and signal lines of such structure formed with a greater length thus increase a resistance thereof and are not suitable for fabricating LCDs display of larger size. Moreover, as the fabrication steps illustrat in FIGS. 1A-1F, an additional conductive layer 114 is thus formed over the conductive line 102 increasing a thickness thereof to thereby reduce overall resistance and signal loss thereof. The above process takes six photolithography steps, however, and makes the process more time consuming. Thus, a simplified array substrate process with less photolithography steps is desirable for display device fabrication.